1. Field of the Invention
The invention relates to computer technology, particularly it concerns computer systems.
The invention has application in both engineering and technical calculations for space and aviation technologies, geodesy, hydrometeorology and other fields which require high performance computations.
2. Description of the Related Art
There is a known computer system which contains central input-output processors, a switch, a main memory unit, a control panel, peripheral memory devices with control blocks and data transmission processors (SU, A, 692400).
In this system Von Neumann""s principle of data processing is used. Every central processor contains a conforming (conjugating) unit, a block for performing procedures, an indexing block, a block for value retrieving, a block for processing strings, an arithmetic-logical unit, a block of the basic registers, a unit for instructions forming, a control unit, a unit for the distribution of stack addresses, a buffering stack of operands, an associative memory unit, a unit for transformation of the mathematical addresses into the physical ones, a block of memory for buffering instructions, a block for analysis of interrupts.
The arithmetic-logical unit includes: blocks for multiplication, addition, division, code transformation and logical operation performing. These blocks work in parallel and independently from one another, providing parallel data processing within each processor and using the natural parallelism of the programs under execution.
However, implementation of this unit has shown that, in practice, the use of Von Neumann""s principle of computation organization requires high unproductive expenditures of hardware and computing capacity to provide parallel work of several executive devices. These expenditures, first of all, are related to the fact that to form independent sequences of instructions from the program in execution it is necessary to do a preliminary survey of program segments (of the average length up to 30 instructions) and a dynamic planning of executing units loading with the help of special hardware means, which was described in detail (Babayan B.A. xe2x80x9cMain results and perspective of development of the xe2x80x9cElbrusxe2x80x9d architecturexe2x80x9d, Applied Computer Science works collection, vol. 15, Moscow, Finance and Statistics, 1989, pp. 100-131).
Due to this fact the hardware becomes considerably more complicated, having simultaneously a low real increase of performance. Parallelism of program processing on several executive devices is restricted and does not spread on the whole program (the segments of parallel processing do not exceed 10-20 instructions). Moreover, the process of extraction of instructions from the program for parallel execution itself requires a large amount of additional hardware and working time of the processor. This is another factor of the decrease in performance.
There is a known device which contains units of common memory, units of central input-output processors, using Von Neumann""s principle of computation processing and parallel work of several executive devices, being parts of central processors. This device achieves program processing parallelism by means of forming an extensive instruction which includes operations for the simultaneous start of several arithmetic units (SU, A, 1777148).
Formation of such an instruction is conducted by static operation planning during the program translation stage. Here, the number of operations of the instruction being executed in parallel is limited (it does not exceed 7).
However, this device does not achieve high performance based on the internal parallelism of the programs in execution because of limited parallelism of operations in execution in the device and a cessation of execution when all the operands necessary for a computation are not available. This problem arises from the restrictions set by the translator and also in the case when the variable position in memory depends on computation conditions. Also, this device has a complicated translator structure and a large amount of the hardware to conduct local parallelism of computation.
There is a known computer system which contains a switch and N processor units. In such a system the first control outputs and address outputs of the i-th processor unit (i=1, . . . ,N) are connected correspondingly with the i-th input of the first control input group and with the i-th input of the group of the address switch inputs. The first and second informational outputs of the i-th processor unit are connected with the corresponding i-th input of the group of informational switch inputs. The first informational, address, control and the second informational, address, control inputs of the i-th processor unit are connected with the first and second informational system inputs. The first control input of this system is connected with the control switch input and with the third control input of the i-th processor unit. The switch control output is connected with the fourth control input of the i-th processor unit. The third informational output of this unit is connected with the first informational output of the system. The computer system can have a second informational output and a third informational input (U.S. Pat. No. 4,814,978).
For computation organization this system uses the data flow principle, which provides effective loading for each processor unit and high total performance. This is achieved by means of parallel instruction execution in all sections of the program and is supported by a programmable computation organization. The program is mapped as a graph, each node of which is an instruction and arcs show the direction of data transmission. Each of the processor units, mutually connected through the switch, executes a local section of the program. The processor units work in parallel and the necessary synchronization between sections of the program is carried out by means of the data transmit through the switch. Parallelism is achieved by the partition of the program during translation into separate linked sections, which leads to a waste of time and adecrease in device performance. Thus, device performance depends greatly on the programming system capability to segregate sections (sub-programs), which are weakly linked to one another. in the original program and is quite time-consuming on the user (programmer) side.
These disadvantages do not allow the full internal parallelism of the programs in execution to be realized in this device and as a result do not achieve high performance based on this parallelism and the data flow principle.
The invention is based on the problem of creating a computer system which would achieve increased performance by means of simultaneous access of each processor unit to the entire program in execution and through automation of the process of computational means distribution.
The problem is solved this way. The computer system contains a switch, N processor units, a second informational output and a third informational input. The first control output and address output of the i-th processor unit (i=1 . . . N) are connected correspondingly with the i-th input of the first group of switch control inputs and with the i-th input of the group of switch address inputs. The first and second informational outputs of the i-th processor unit are connected with the corresponding input of the group of switch informational inputs. The first informational, address, and control inputs and the second informational, address, and control inputs of the i-th processor unit are connected with the first and second informational inputs of the system. The first control input of the system is connected with the control input of the switch and with third control input of the i-th processor unit. The control output of the switch 2 is connected with the fourth control input of the i-th processor unit. The third informational output of the i-th processor unit is connected with the first informational output of the system.
According to the invention,
1. The computer system contains an auxiliary switch, N modules of associative memory and a buffering block. The first control, first informational, second control and second informational outputs of the i-th group of exchange outputs of the auxiliary switch are connected correspondingly with the fifth control, third informational, sixth control and fourth informational inputs of the i-th processor unit. The first group of control outputs of the auxiliary switch is connected with the first group of control inputs of the buffering block. The second group of control outputs of the auxiliary switch is connected with the second group of control inputs of the buffering block. The control inputs of the auxiliary switch and of the buffering block and the first control input of each module of associative memory are connected with the control input of the system. The i-th inputs of the first and second groups of control inputs of the auxiliary switch are connected correspondingly with the second and third control outputs of the i-th processor unit. The seventh and eighth control inputs of the i-th processor unit are connected correspondingly with the i-th outputs of the first and second groups control outputs of the buffering block. The third group of control outputs and the first group of the informational outputs of the buffering block are connected correspondingly with the third group of control inputs and the first group of informational inputs of the auxiliary switch. The second group of informational outputs of the buffering block is connected with the second informational output of the system. The fourth group of control inputs of the auxiliary switch is connected with the fourth group of control outputs of the buffering block. The i-th input of the first group of informational inputs of the buffering block is connected with the fourth and fifth informational outputs of the i-th processor unit. The fourth control output of i-th processor unit is connected with the i-th input of the third group of control inputs of the buffering block. The third group of informational outputs of the buffering block is connected with the second group of informational inputs of the auxiliary switch. The first control output of the i-th module of associative memory is connected with the i-th input of the second group of control inputs of the switch. The i-th output of the group of informational outputs of the switch is connected with the informational input of the i-th module of associative memory. The informational and the second control outputs of the i-th module of associative memory are connected with the i-th inputs of the second group of informational inputs and the fourth group of control inputs of the buffering block. The third group of informational inputs of the buffering block is connected with the third informational input of the system. And, the i-th output of the group of control outputs of the switch is connected with the second control input of the i-th module of associative memory.
2. Each processor unit, according to the invention, may contain the first and second switches, the first and second control units, an executive device for instruction processing and an executive device for operand processing. The first and second control inputs of the first switch are connected with the first and second control outputs of the first control unit of control. The third control output of the first control unit is connected with the first control input of the executive device for instruction processing. The first and the second control outputs of the second control unit are connected with the first and second control inputs of the second switch. The first informational input of the second switch is connected with the address output of the executive device for instruction processing, the first informational output of the executive device for instruction processing is connected with the second informational input of the second switch and the first informational input of the first switch. The second informational output of the executive device for instruction processing is connected with the second informational input of the first switch and the third informational input of the second switch. The first control output of the executive device for instruction processing is connected with the first control input of the first control unit. The fourth control output of the first control unit is connected with the first control input of the executive device for operand processing. The first control output of the executive device for operand processing is connected with the second control input of the first control unit. The first control input of the second control unit is connected with the second control output of the executive device for operand processing. The second control output of the executive device for instruction processing is connected with the second control input of the second control unit. The second control input of the executive device for instruction processing is connected with the third control output of the second control unit. The fourth control output of the second control unit is connected with the second control input of the executive device for operand processing. The fourth informational input of the second switch is connected with the address output of the executive device for operand processing. The first informational output of the executive device for operand processing is connected with the fifth informational input of the second switch and the third informational input of the first switch. The second informational output of the executive device for operand processing is connected with the fourth informational input of the first switch and with the sixth informational input of the second switch. The first, second and third informational outputs of the second switch are the address output, the first informational output and second informational output of the processor unit respectively. The third informational outputs of the executive device for instruction processing and of the executive device for operand processing are connected with the third informational output of the processor unit. The fourth and fifth informational outputs of the processor unit are respectively the first and second informational outputs of the first switch. The fifth control output of the second control unit is connected with the first control output of the processor unit. The second and third control outputs of the processor unit are the third control outputs of the executive device for instruction processing and of the executive device for operand processing respectively. The fourth control output of the processor unit is connected with the fifth control output of the first control unit. The first informational, address and control inputs of the processor unit are the first informational, address and the third control inputs of the executive device for instruction processing respectively. The second informational, address and control inputs of the processor unit are connected correspondingly with the first informational, address and the third control inputs of the executive device for operand processing. The fourth control input of the executive device for operand processing and the fourth control input of the executive device for instruction processing are connected with the third control input of the processor unit. The fourth control input of the processor unit is connected with the third control input of the second control unit. The third informational input of the processor unit is the second informational input of the executive device for instruction processing. The fifth control input of the executive device for instruction processing is the fifth control input of the processor unit. The fourth informational and the sixth control inputs of the processor unit are connected with the second informational and the fifth control inputs of the executive device for operand processing respectively. And, the seventh and eighth control inputs of the processor unit are connected with the third and fourth control inputs of the first control unit respectively.
3. The auxiliary switch, according to the invention, may contain the first and second control units and the first and second switching units. The first groups of the control outputs of the first and second control units are connected with the first and second groups of the control outputs of the auxiliary switch respectively. The first and second control outputs of the i-th group of exchange outputs of the auxiliary switch are connected with the i-th outputs of the second group of the control outputs of the first and second control units respectively. The control inputs of the first and second control units are connected with the control input of the auxiliary switch. The first and second groups of the informational inputs of the auxiliary switch are connected with the groups of the informational inputs of the first and second switching units respectively. The i-th outputs of the group of the informational outputs of the first and second switching units are connected correspondingly with the first and second informational outputs of the i-th group of the exchange outputs of the auxiliary switch. The first and second groups of the control inputs of the auxiliary switch are connected with the first groups of the control inputs of the first and second control units respectively. The groups of the control outputs of the first and second switching units are connected correspondingly with the second groups of the control inputs of the first and the second control units. The third groups of the control inputs of the first and the second control units are connected correspondingly with the third and fourth groups of the control inputs of the auxiliary switch. And, the third groups of the control outputs of the first and second control units are connected with the first groups of the control inputs of the first and second switching units respectively. The second group of the control inputs of each of these units is connected correspondingly with the fourth group of the control outputs of the first and second control units.
4. The buffering block, according to the invention, may contain the group of buffering units. The first, second and third control outputs of the i-th buffering unit are connected with the i-th outputs of the first, second and third groups of the control outputs of the buffering block respectively. The i-th inputs of the first and second groups of the control inputs of the buffering block are connected with the first and second control inputs of the i-th buffering unit respectively. The fourth control output of the buffering unit is connected with the i-th output of the fourth group of the control outputs of the buffering block. The control input of the buffering block is connected with the third control input of each of the buffering units. The i-th inputs of the third and fourth groups of the control inputs of the buffering block are connected with the fourth and fifth control inputs of the i-th buffering unit respectively. The first, second and third informational outputs of the buffering units are connected correspondingly with the i-th outputs of the first, second and third groups of the informational outputs of the buffering block. The i-th inputs of the first, second and third groups of the informational inputs of the buffering block are connected with the first, second and third informational inputs of the i-th buffering unit respectively.